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Addendum
DS1, 2003-07-02 QuadFALC(R) Quad E1/T1/J1 Framer and Line Interface Component for Long- and Short-Haul Applications PEF 22554 HT/E, Version 2.1
Abstract This document is an Addendum to the PEF 22554 HT/E, QuadFALC(R), Version 2.1 Data Sheet DS1, release date 2002-09. It describes data that has to be changed or added.
1
Referenced Standards
Page 5, Related Documentation In addition to the standards listed in the Data Sheet, the device complies also with: * * * ITU-T G.705 ITU-T G.733 ITU-JT G.733
Revision History: Previous Version: Major Changes:
-/-/-
Addendum
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QuadFALC(R) V2.1 PEF 22554 HT/E
Logic Symbol for BGA Package
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Logic Symbol for BGA Package
Page 23, Chapter 1.2, Logic Symbol Due to the slight difference (number of power supply and ground connections) between the TQFP package and the BGA package, a separate drawing is provided for the BGA.
VSSP VDDP(2:1) RCLK(4:1) MCLK SYNC SEC/FSC
Receive Line Interface Boundary Scan Interface
VDDR(4:1) VSSR(4:1) RL1/RDIP/ROID(4:1) RL2/RDIN/RCLK(4:1) TDI TMS TCK TRS TDO
SCLKR(4:1) RDO(4:1) RPA(4:1) RPB(4:1) RPC(4:1) RPD(4:1)
Receive System Interface
QuadFALC(R) PEF 22554 V2.1 P-TQFP-144
SCLKX(4:1) XDI(4:1) XPA(4:1) XPB(4:1) XPC(4:1) XPD(4:1) CS WR/RW RD/DS BHE/BLE ALE DBW IM RES INT Transmit System Interface
Transmit Line Interface
VDDX(4:1) VSSX(4:1) XL1/XDOP/XIOD(4:1) XL2/XDON/XFM(4:1)
VSEL VDDC(2:1) VDD(5:1) VSS(6:1)
D(15:0)
A(9:0)
Microprocessor Interface
F0263_TQFP_22554
Figure 1
Addendum
Logic Symbol (TQFP Package)
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Logic Symbol for BGA Package
VSSP VDDP(2:1) RCLK(4:1) MCLK SYNC SEC/FSC
Receive Line Interface Boundary Scan Interface
VDDR(4:1) VSSR(4:1) RL1/RDIP/ROID(4:1) RL2/RDIN/RCLK(4:1) TDI TMS TCK TRS TDO
SCLKR(4:1) RDO(4:1) RPA(4:1) RPB(4:1) RPC(4:1) RPD(4:1)
Receive System Interface
QuadFALC(R) PEF 22554 V2.1 P-BGA-160
SCLKX(4:1) XDI(4:1) XPA(4:1) XPB(4:1) XPC(4:1) XPD(4:1) CS WR/RW RD/DS BHE/BLE ALE DBW IM RES INT Transmit System Interface
Transmit Line Interface
VDDX(8:1) VSSX(8:1) XL1/XDOP/XIOD(4:1) XL2/XDON/XFM(4:1)
VSEL VDDC(2:1) VDD(9:1) VSS(10:1)
D(15:0)
A(9:0)
Microprocessor Interface
F0263_BGA_22554
Figure 1A
Logic Symbol (BGA Package)
Addendum
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JTAG Ball Names
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JTAG Ball Names
Page 52, Chapter 2.2, Pin Definitions and Functions The BGA ball numbers are missing for the JTAG pins. They are as shown below. Table 5 Pin No. Pin Definitions - Miscellaneous Ball No. Symbol Input Output Supply I + PU Function
Boundary Scan/Joint Test Access Group (JTAG) 131 B6 TRS Test Reset for Boundary Scan (active low). If not connected, an internal pullup transistor ensures high input level. If the JTAG boundary scan is not used, this pin must be connected to RES or VSS. Test Data Input for Boundary Scan If not connected an internal pullup transistor ensures high input level. Test Mode Select for Boundary Scan If not connected an internal pullup transistor ensures high input level. Test Clock for Boundary Scan If not connected an internal pullup transistor ensures high input level. Test Data Output for Boundary Scan
112
D11
TDI
I + PU
141
D5
TMS
I + PU
140
C4
TCK
I + PU
113
C11
TDO
O
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Boundary Scan
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4.1
Boundary Scan
JTAG Instructions
Page 63, Chapter 3.4.2, Boundary Scan Interface The TAP controller instruction codes 01010101B and 01010100B have been added. Both are reserved for device tests and shall not be used.
4.2
JTAG ID
Page 427, Chapter 11.4.2, JTAG Boundary Scan Interface The correct Boundary Scan IDCODE field is: 0001 0000 0000 1000 1110 0000 1000 0011 (Version = 1H, Part Number = 008EH)
5
RCLK Clock Multiplexing
Page 65/124, Chapter 4.1/5.1, Receive Path in E1 or T1/J1 Mode Some details have been added to the figure showing the clock multiplexing options for RCLK.
recovered clock channel 1 recovered clock channel 2 recovered clock channel 3 recovered clock channel 4
A
DCO-R channel 1
C B C RCLK1 RCLK2
A
DCO-R channel 2
A: controlled by CMR1.DRSS(1:0) B: controlled by GPC1.R1S(1:0) C: controlled by CMR1.RS(1:0)
A
DCO-R channel 3
C
RCLK3
A
DCO-R channel 4
C
RCLK4
F0131_2
Figure 17/46
Receive Clock Selection (E1/T1/J1)
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Bipolar Violation Detection
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Bipolar Violation Detection
Page 68, Chapter 4.1.6, Receive Line Coding in E1 Mode The HDB3 line code or the AMI coding is provided for the data received from the ternary or the dual rail interface. All code violations that do not correspond to zero substitution rules are detected, resulting in an increment of the 16-bit code violation counter. If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is neither detected nor counted and the substitution pattern is replaced by the corresponding zero pattern. In case of the optical interface a selection between the NRZ code and the CMI Code (1T2B) with HDB3 or AMI postprocessing is provided. If CMI code is selected the receive route clock is recovered from the data stream. The CMI decoder does not correct any errors. In case of NRZ coding data is latched with the falling edge of signal RCLKI. The HDB3 code is used along with double violation detection or extended code violation detection (selectable by FMR0.EXZE). In AMI code all code violations are detected. The detected errors increment the code violation counter (16 bits length). Page 127, Chapter 5.1.6, Receive Line Coding in T1/J1 Mode The B8ZS line code or the AMI (ZCS, zero code suppression) coding is provided for the data received from the ternary or the dual rail interface. All code violations that do not correspond to zero substitution rules are detected, resulting in an increment of the 16-bit code violation counter. If a bit error causes a code violation that leads to a valid substitution pattern, this code violation is neither detected nor counted and the substitution pattern is replaced by the corresponding zero pattern. The detected errors increment the code violation counter (16 bits length).
Addendum
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Signaling Marker Diagrams
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Signaling Marker Diagrams
Page 180/181, Chapter 5.5.2, Transmit System Interface The following diagrams have been modified for clarity.
125 s
SYPX
SCLKX T TS24 XDI XSIG XSIG TS1 TS2 TS24 01 23456 7F A B CD ABAB ESF F12 45 67F01 23456 70123 4567 A B CD ABAB T F ABCD ABAB A B CD ABAB A B CD AB AB
= Tim slot offset (RC0, RC1) e = FS/DL-bit (XDI only) = ESF signaling bits for tim slots 1...24 e read only during last fram of a m e ultifram e, = F12 signaling bits for tim slots 1...24 e read only during last fram of a m e ultifram (bit positions 4/5) e
F 0137
Figure 71
1.544 MHz Transmit Signaling Highway (T1/J1)
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Signaling Marker Diagrams
Multiframe n (F12 for example)
Frame 1 RDO XDI
Frame 6
Frame 12
Frame 1
RMFB XMFB
A: Channel Translation Mode 0 RDO XDI
24
FS/ DL
123
456
789
19 20 21
22 23 24
FS/ DL
1
RSIGM1) XSIGM B: Channel Translation Mode 1 RDO XDI RSIGM1) XSIGM Notes: 1) RSIGM and XSIGM are programmed to mark only channel 24 in this example (via RTR(4:1) and TTR(4:1)).
F0267_1
FS/ DL
123456
19 20 21 22 23 24
FS/ DL
1
Figure 72
Signaling Marker for CAS/CAS-CC Applications (T1/J1)
Addendum
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Clock Mode Selection
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Clock Mode Selection
Page 194/200, Chapter 6.3 and Chapter 7.3, Device Initialization E1 and T1/J1 The following text has been added: The clock mode must be programmed according to the selected MCLK frequency before any XL1/2 output is enabled (while the outputs are not yet activated by selection of the line coding). Otherwise the output pulse width might not match the pulse mask requirements. Page 277, Chapter 9.2 and Page 384, Chapter 10.2, Clock Mode Register programming for E1 and T1/J1 The following text has been added/corrected (for E1 and T1/J1 operation): Attention: Write operations to GCM5 and/or GCM6 register initiate a PLL reset (see below) and must be performed before any port configuration is done. If this is not possible set LIM01.DRS (if not set) of every channel separately before writing to these registers and reset LIM01.DRS (if it was not set before) after these write operations.
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Device Initialization
Page 192, Table 46, Initial Values after Reset (E1) The second row shall read: 2.048 8.192 MHz system clocking rate... Page 194, Table 47, Initialization Parameters (E1) The row "Framing additions" shall read: RC0RC1.ASY4, RC0RC1.SWD
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HDLC Handling
Page 221/321, Chapter 9.2/10.2, Register bit CMDR.RMC Confirmation from CPU to QuadFALC that the current frame or data block has been fetched following an RPF or RME interrupt, thus the occupied space in the RFIFO can be released. While the FIFO is empty, RMC must not be set. If RMC is given while RFIFO is already cleared, the next incoming data block is cleared instantly, although interrupts are generated. This might lead to incorrect software behaviour.
Addendum
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Port RMFB Configuration
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Port RMFB Configuration
Page 269/375, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: RMFB is only valid, if the receive buffer is not bypassed.
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Port RSIG Configuration
Page 270/376, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: RSIG is only valid, if the receive buffer is not bypassed.
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Port XMFS Configuration
Page 270/376, Chapter 9.2/10.2, Register Description, PC(4:1) The following text has been added: The activity level of port XMFS can be selected to be active high or active low by programming PC5.CXMFS. This bit must not be set, if XMFS is not enabled as an input. XMFS input selection is done by programming one of the Transmit Multifunction Ports, using registers PC4(4:1).XPC(3:0). Note: XMFS must not be used together with SYPX on different Multifunction Ports.
14
Port RFSP Configuration
Page 376, Chapter 10.2, Register Description, PC(4:1) in T1/J1 mode The description of register bit PC(4:1).RPC(2:0) = 111 in T1/J1 mode shall read as: "This marker is active low for 488 648 ns with a frequency of 8 kHz."
Addendum
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Absolute Maximum Ratings
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Absolute Maximum Ratings
Page 420, Chapter 11.1, Absolute Maximum Ratings The allowed voltage range has been increased. The following values and the text below the table have changed: Parameter IC supply voltage (pads, digital) IC supply voltage (core, digital) IC supply voltage PLL (analog) IC supply voltage receive (analog) IC supply voltage transmit (analog) Voltage on any pin with respect to ground1) Voltage on RL1/RL2 with respect to ground
1)
Symbol
Limit Values - 0.3 to 2.4
Unit V
VDD VDDC VDDP VDDR VDDX VPAD VRL1/RL2
- 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.3 0.5 to 3.6 4.5 V - 0.8 to 4.5 V
except VDDC and VRL1/RL2
Attention: Absolute Maximum Ratings are stress ratings only, and functional operation and reliability under conditions beyond those defined in the normal operating conditions is not guaranteed. Stresses above the maximum ratings are likely to cause permanent damage to the device while extended exposure to conditions outside the operating range may have an impact on component life time.
Addendum
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DC Characteristics
16
DC Characteristics
Page 422/423, Chapter 11.3, DC Characteristics The transmitter output maximum leakage value and receiver maximum input voltage have been changed. Parameter Transmitter leakage current Symbol Limit Values Min. Max. 15.0 30.0 15.0 30.0 Receiver peak voltage of a VR12 mark (at RL1 or RL2) Receiver differential peak voltage of a mark (between RL1 and RL2)
1) 2)
Unit A A V V
Notes XL1/2 = VDDX; XPM2.XLT = 1 XL1/2 = VSSX; XPM2.XLT = 1 RL1, RL2; RZ signals only2) RL1, RL2; RZ signals only2)
ITL
-0.45 -0.751)
3.8 4.11) VDDR +0.3 4.00 4.631)
VR
Limit values must only be applied during T1 pulse over-/undershoot according to ANSI T1.403-1999. RZ = return to zero
Addendum
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System Interface Marker Timing (Receive)
17
System Interface Marker Timing (Receive)
Page 437, Chapter 11.4.6, AC Characteristics, System Interface The timing figure has been modified for clarity. The timing values have been corrected.
positive edge timing 1) negative edge timing 1) positive edge timing 1) negative edge timing 1)
SCLKR
1(A) 2(A)
data valid
RDO RSIG RSIGM DLR RFM RMFB FREEZE
1)
1(A)
data valid
2(A)
active edge can be programmed to be positive or negative
possible negative delay values are not explicitely drawn
F0011
Figure 99 Table 79 No.
System Interface Marker Timing (Receive) System Interface Marker Timing Parameter Values Limit Values Min. Typ. Max. 35 45 ns ns Unit
Parameter
SCLKR Input Mode 1 2 RDO delay RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay RDO delay RSIGM, RMFB, DLR, RFM1), FREEZE, RSIG marker delay 0 0
SCLKR Output Mode 1A 2A -55 0 -55 0 9 9 -20 20 -20 20 ns ns
SCLKR can be input or output.
1)
Timing for RMF is valid only for active high polarity selection.
Addendum
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SYPR/SYPX Timing
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SYPR/SYPX Timing
Page 438/439, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below.
1(A) active edge
SCLKR SCLKX
2(A) 3(A) 4(A)
SYPR SYPX
inactive 5(A)
active low
6(A)
7(A)
XMFS
inactive
active low
F0012
Figure 100 Table 80 No.
SYPR/SYPX Marker Timing SYPR/SYPX Timing Parameter Values Limit Values Min. Typ. Max. 648 ns ns ns ns ns ns ns 648 ns ns
DS1, 2003-07-02
Parameter
Unit
SCLKR Input Mode 1 2 3 4 5 6 7 1A 2A SCLKR period (t1) SYPR/SYPX inactive setup time SYPR/SYPX setup time SYPR/SYPX hold time XMFS inactive setup time XMFS setup time XMFS hold time SCLKR period (t1) SYPR/SYPX inactive setup time
14
61 1 x t1 5 15 1 x t1 5 15 61 1 x t1
SCLKR Output Mode
Addendum
QuadFALC(R) V2.1 PEF 22554 HT/E
SYPR/SYPX Timing Table 80 No. SYPR/SYPX Timing Parameter Values (cont'd) Limit Values Min. SCLKR Output Mode 3A 4A 5A 6A 7A SYPR/SYPX setup time SYPR/SYPX hold time XMFS inactive setup time XMFS setup time XMFS hold time 10 0 0 10 1 x t1 10 0 0 10 ns ns ns ns ns Typ. Max. Unit
Parameter
Addendum
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Marker Output Timing Parameters
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Marker Output Timing Parameters
Page 440, Chapter 11.4.6, AC Characteristics, System Interface The output timing has been corrected as shown in the table below.
active edge1)
SCLKR SCLKX
1(A)
XMFB DLX XSIGM
Figure 101 Table 81 No.
1)
active edge can be programmed to be positive or negative
F0013
System Interface Marker Timing System Interface Marker Timing Parameter Values Limit Values Min. Typ. Max. 100 0 9 -20 20 ns ns Unit
Parameter
SCLKR Input Mode 1 1A XMFB, DLX, XSIGM delay XMFB, DLX, XSIGM delay SCLKR Output Mode
Addendum
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XDI/XSIG Timing Parameters
20
XDI/XSIG Timing Parameters
Page 441, Chapter 11.4.6, AC Characteristics, System Interface The timing has been corrected as shown in the table below.
active edge1)
SCLKR SCLKX
1(A) 2(A)
XDI
3(A) 4(A)
XSIG
1)
active edge can be programmed to be positive or negative
F0014
Figure 101 Table 81 No.
XDI/XSIG Marker Timing XDI/XSIG Timing Parameter Values Limit Values Min. Typ. Max. ns ns ns ns ns ns Unit
Parameter
SCLKR Input Mode 1 2 3 4 1A 2A XDI setup time XDI hold time XSIG setup time XSIG hold time XDI setup time XDI hold time 5 15 5 15 10 0 20 10
SCLKR Output Mode
Addendum
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SYNC Input Timing Parameters Table 81 No. 3A 4A XDI/XSIG Timing Parameter Values (cont'd) Limit Values Min. XSIG setup time XSIG hold time 10 0 20 10 Typ. Max. ns ns Unit
Parameter
21
SYNC Input Timing Parameters
Page 446, Chapter 11.4.6, AC Characteristics, System Interface The input timing has been relaxed as shown in the table below.
1 SYNC
Figure 107 Table 87 No. 1 2 SYNC Timing
2
F0125
SYNC Timing Parameter Values Limit Values Min. Typ. Max. % ns % ns 30 122 30 122 Unit
Parameter SYNC high time SYNC low time
22
Typographical Errata
Page 57, Table 7: "BHE" should read "BHE" Page 57, Table 8: "BLE" should read "BLE" Page 256/361, FLLB = 1: The line loopback code is transmitted in unframed mode. LLB code does not overwrite the FS/DL-bits.
Addendum
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